NVIDIA

NVIDIA Jetson Orin Nano Super Dev Kit pinout

Name: NVIDIA Jetson Orin Nano Super Dev Kit pinout with per-pin electrical limits
Creator: Xirkit
License: https://creativecommons.org/licenses/by/4.0/

All 40 pins of the NVIDIA Jetson Orin Nano Super Dev Kit, each mapped to the Jetson Orin Nano 8GB pad it routes to, with its functions and — for 28 pins — the voltage and current limits from the chip datasheet.

40 pins28 with electrical limits4 power out28 gpio8 ground

NVIDIA Jetson Orin Nano Super Dev Kit pins, functions and electrical limits

VIH/VIL: input thresholds · VOH/VOL: output levels · IOH/IOL: output current. Values apply to the chip pad each pin routes to, under the conditions cited in the source.
Pin	Position	Kind	Chip pad	Functions	VIH	VIL	VOH	VOL	IOH	IOL	5 V tolerant	Abs max	Source
3.3V	J12 · 1	power out		power_out
5.0V	J12 · 2	power out		power_out
I2C1_SDA	J12 · 3	gpio	I2C1_SDA	I2C1_SDA, I2C #1 Data	2.64–3.63 V	≤ 0.66 V	≥ 2.31 V	≤ 0.99 V		≤ 2 mA	no	-0.5–3.63 V	p.27
5.0V	J12 · 4	power out		power_out
I2C1_SCL	J12 · 5	gpio	I2C1_SCL	I2C1_SCL, I2C #1 Clock	2.64–3.63 V	≤ 0.66 V	≥ 2.31 V	≤ 0.99 V		≤ 2 mA	no	-0.5–3.63 V	p.27
GND	J12 · 6	ground		ground
GPIO09	J12 · 7	gpio	GPIO09	GPIO09, Audio Primary Clock					≤ 20 uA	≤ 20 uA			p.26 table 26_1
UART1_TXD	J12 · 8	gpio	UART1_TXD	UART1_TXD, UART #1 Transmit					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 9	ground		ground
UART1_RXD	J12 · 10	gpio	UART1_RXD	UART1_RXD, UART #1 Receive					≤ 20 uA	≤ 20 uA			p.26 table 26_1
UART1_RTS*	J12 · 11	gpio	UART1_RTS*	UART1_RTS*, UART #2 Request to Send					≤ 20 uA	≤ 20 uA			p.26 table 26_1
I2S0_SCLK	J12 · 12	gpio	I2S0_SCLK	I2S0_SCLK, Audio I2S #0 Clock					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI1_SCK	J12 · 13	gpio	SPI1_SCK	SPI1_SCK, SPI #1 Shift Clock					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 14	ground		ground
GPIO12	J12 · 15	gpio	GPIO12	GPIO12					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI1_CSI1*	J12 · 16	gpio	SPI1_CS1*	SPI1_CSI1*, SPI #1 Chip Select #1 Bidir/Output					≤ 20 uA	≤ 20 uA			p.26 table 26_1
3.3V	J12 · 17	power out		power_out
SPI1_CSI0*	J12 · 18	gpio	SPI1_CS0*	SPI1_CSI0*, SPI #0 Chip Select #0 Bidir/Output					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI0_MOSI	J12 · 19	gpio	SPI0_MOSI	SPI0_MOSI, SPI #0 Primary Out/Secondary In					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 20	ground		ground
SPI0_MISO	J12 · 21	gpio	SPI0_MISO	SPI0_MISO, SPI #0 Primary In/Secondary Out					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI1_MISO	J12 · 22	gpio	SPI1_MISO	SPI1_MISO, SPI #1 Primary In/Secondary Out					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI0_SCK	J12 · 23	gpio	SPI0_SCK	SPI0_SCK, SPI #0 Shift Clock					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI0_CS0*	J12 · 24	gpio	SPI0_CS0*	SPI0_CS0*, SPI #0 Chip Select #0 Bidir/Output					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 25	ground		ground
SPI0_CS1*	J12 · 26	gpio	SPI0_CS1*	SPI0_CS1*, SPI #0 Chip Select #1 Bidir/Output					≤ 20 uA	≤ 20 uA			p.26 table 26_1
I2C0_SDA	J12 · 27	gpio	I2C0_SDA	I2C0_SDA, I2C #0 Data	2.64–3.63 V	≤ 0.66 V	≥ 2.31 V	≤ 0.99 V		≤ 2 mA	no	-0.5–3.63 V	p.27
I2C0_SCL	J12 · 28	gpio	I2C0_SCL	I2C0_SCL, I2C #0 Clock	2.64–3.63 V	≤ 0.66 V	≥ 2.31 V	≤ 0.99 V		≤ 2 mA	no	-0.5–3.63 V	p.27
GPIO01	J12 · 29	gpio	GPIO01	GPIO01, General Purpose Clock #0					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 30	ground		ground
GPIO11	J12 · 31	gpio	GPIO11	GPIO11, General Purpose Clock #1					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GPIO07	J12 · 32	gpio	GPIO07	GPIO07, PWM					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GPIO13	J12 · 33	gpio	GPIO13	GPIO13, PWM					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 34	ground		ground
I2S0_FS	J12 · 35	gpio	I2S0_FS	I2S0_FS, Audio I2S #0 Field Select					≤ 20 uA	≤ 20 uA			p.26 table 26_1
UART1_CTS*	J12 · 36	gpio	UART1_CTS*	UART1_CTS*, UART #1 Clear to Send					≤ 20 uA	≤ 20 uA			p.26 table 26_1
SPI1_MOSI	J12 · 37	gpio	SPI1_MOSI	SPI1_MOSI, SPI #1 Primary Out/Secondary In					≤ 20 uA	≤ 20 uA			p.26 table 26_1
I2S0_DIN	J12 · 38	gpio	I2S0_DIN	I2S0_DIN, Audio I2S #0 Data in					≤ 20 uA	≤ 20 uA			p.26 table 26_1
GND	J12 · 39	ground		ground
I2S0_DOUT	J12 · 40	gpio	I2S0_DOUT	I2S0_DOUT, Audio I2S #0 Data Out					≤ 20 uA	≤ 20 uA			p.26 table 26_1

NVIDIA Jetson Orin Nano Super Dev Kit overview · All development boards