Seeed Studio · structured pinout

Seeed Studio XIAO ESP32C3 pinout

All 22 pins of the Seeed Studio XIAO ESP32C3, each mapped to the ESP32-C3FH4 pad it routes to, with its functions and — for 16 pins — the electrical limits from the chip datasheet. Every number cites its page and table.

22 pins documented16 with electrical limits15 gpio1 power out3 ground2 power in1 controlcomplete pinout
Pin table

Seeed Studio XIAO ESP32C3 pins, functions and electrical limits

Markdown · JSON
VIH/VIL: input thresholds · VOH/VOL: output levels · IOH/IOL: output current. Values apply to the chip pad each pin routes to, under the conditions cited in the source.
PinPositionKindChip padFunctionsVIHVILVOHVOLIOHIOL5 V tolerantAbs maxSource
D0J2 · 1gpioGPIO2Analog, ADC1_CH2, GPIO2, FSPIQ, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D1J2 · 2gpioGPIO3Analog, ADC1_CH3, GPIO3, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D2J2 · 3gpioGPIO4Analog, ADC1_CH4, FSPIHD, MTMS, GPIO4, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D3J2 · 4gpioGPIO5Analog, ADC2_CH0, FSPIWP, MTDI, GPIO5, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D4J2 · 5gpioGPIO6SDA, FSPICLK, MTCK, GPIO6, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D5J2 · 6gpioGPIO7SCL, FSPID, MTDO, GPIO7, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D6J2 · 7gpioGPIO21TX, U0TXD, GPIO21, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D7J1 · 8gpioGPIO20RX, U0RXD, GPIO20, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D8J1 · 9gpioGPIO8SCK, GPIO8, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D9J1 · 10gpioGPIO9MISO, BOOT button, GPIO9, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
D10J1 · 11gpioGPIO10MOSI, FSPICS0, GPIO10, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
3V3J1 · 12power outpower_outp.2 table 2_1
GNDJ1 · 13groundground
5VJ1 · 14power inpower_inp.2 table 2_1
TP1bottom_pads · TP1groundground
TP2bottom_pads · TP2gpioGPIO4MTMS, GPIO4, FSPIHD, ADC1_CH4, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
TP3bottom_pads · TP3gpioGPIO5MTDI, GPIO5, FSPIWP, ADC2_CH0, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
TP4bottom_pads · TP4gpioGPIO6MTCK, GPIO6, FSPICLK, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
TP5bottom_pads · TP5gpioGPIO7MTDO, GPIO7, FSPID, GPIO matrix (any routable peripheral signal)2.475–3.6 V-0.3–0.825 V≥ 2.64 V≤ 0.33 V40 mA typ28 mA typno-0.3–3.6 VESP32-C3 datasheet p.55 table 55_2
TP6bottom_pads · TP6controlCHIP_ENen2.475–3.6 V-0.3–0.825 VnoESP32-C3 datasheet p.55 table 55_2
BAT+bottom_pads · BAT+power inpower_inp.2 table 2_1
GNDbottom_pads · GND padgroundground
Answers from the record

Seeed Studio XIAO ESP32C3 pinout FAQ

What microcontroller does the Seeed Studio XIAO ESP32C3 use?

The Seeed Studio XIAO ESP32C3 is built around the ESP32-C3FH4, alongside TLV75733PDBVR.

How many GPIO pins does the Seeed Studio XIAO ESP32C3 have?

11 GPIO pins are exposed. Xirkit documents 22 board pins, 16 of them with pin-level electrical limits.

Are the Seeed Studio XIAO ESP32C3 I/O pins 5 V tolerant?

No. The I/O pins are not 5 V tolerant — they run at 3.3 V logic; use a level shifter for 5 V signals. Input-high threshold: 2.475–3.6 V.

How much current can a Seeed Studio XIAO ESP32C3 GPIO pin source?

Documented output-high current per pin: 40 mA typ. Values are traced to the chip datasheet; see the pinout table for per-pin limits and conditions.

What voltage powers the Seeed Studio XIAO ESP32C3?

Supply range 3.7–5 V. Power inputs: 5V, BAT+.

Go deeper

Related data

Looking for something else? Browse every structured part.

Sign up