Seeed Studio · structured pinout

Seeed Studio XIAO RP2040 pinout

Name: Seeed Studio XIAO RP2040 pinout with per-pin electrical limits
Creator: Xirkit

All 20 pins of the Seeed Studio XIAO RP2040, each mapped to the RP2040 pad it routes to, with its functions and — for 14 pins — the electrical limits from the chip datasheet. Every number cites its page and table.

20 pins documented14 with electrical limits11 gpio2 power in3 ground1 power out2 debug1 controlcomplete pinout

Pin table

Seeed Studio XIAO RP2040 pins, functions and electrical limits

Markdown · JSON

VIH/VIL: input thresholds · VOH/VOL: output levels · IOH/IOL: output current. Values apply to the chip pad each pin routes to, under the conditions cited in the source.
Pin	Position	Kind	Chip pad	Functions	VIH	VIL	VOH	VOL	IOH	IOL	5 V tolerant	Abs max	Source
D0	castellated_edge · L1	gpio	GPIO26	D0, GPIO26, PWM, A0, PIO (any GPIO), SPI1_SCK, UART1_CTS, I2C1_SDA, PWM5_A, SIO, PIO0, PIO1, USB_VBUS_EN, ADC0	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D1	castellated_edge · L2	gpio	GPIO27	D1, GPIO27, PWM, A1, PIO (any GPIO), SPI1_TX, UART1_RTS, I2C1_SCL, PWM5_B, SIO, PIO0, PIO1, USB_OVCUR_DET, ADC1	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D2	castellated_edge · L3	gpio	GPIO28	D2, GPIO28, PWM, A2, PIO (any GPIO), SPI1_RX, UART0_TX, I2C0_SDA, PWM6_A, SIO, PIO0, PIO1, USB_VBUS_DET, ADC2	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D3	castellated_edge · L4	gpio	GPIO29	D3, GPIO29, PWM, A3, PIO (any GPIO), SPI1_CSn, UART0_RX, I2C0_SCL, PWM6_B, SIO, PIO0, PIO1, USB_VBUS_EN, ADC3	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D4	castellated_edge · L5	gpio	GPIO6	D4, GPIO6, PWM, SDA0, PIO (any GPIO), SPI0_SCK, UART1_CTS, I2C1_SDA, PWM3_A, SIO, PIO0, PIO1, USB_OVCUR_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D5	castellated_edge · L6	gpio	GPIO7	D5, GPIO7, PWM, SCL0, PIO (any GPIO), SPI0_TX, UART1_RTS, I2C1_SCL, PWM3_B, SIO, PIO0, PIO1, USB_VBUS_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D6	castellated_edge · L7	gpio	GPIO0	D6, GPIO0, PWM, TX, PIO (any GPIO), SPI0_RX, UART0_TX, I2C0_SDA, PWM0_A, SIO, PIO0, PIO1, USB_OVCUR_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
5V	castellated_edge · R1	power in		power_in									p.4 table 4_1
GND	castellated_edge · R2	ground		ground
3V3	castellated_edge · R3	power out		power_out									p.5
D10	castellated_edge · R4	gpio	GPIO3	D10, GPIO3, PWM, MOSI, PIO (any GPIO), SPI0_TX, UART0_RTS, I2C1_SCL, PWM1_B, SIO, PIO0, PIO1, USB_OVCUR_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D9	castellated_edge · R5	gpio	GPIO4	D9, GPIO4, PWM, MISO, PIO (any GPIO), SPI0_RX, UART1_TX, I2C0_SDA, PWM2_A, SIO, PIO0, PIO1, USB_VBUS_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D8	castellated_edge · R6	gpio	GPIO2	D8, GPIO2, PWM, SCK, PIO (any GPIO), SPI0_SCK, UART0_CTS, I2C1_SDA, PWM1_A, SIO, PIO0, PIO1, USB_VBUS_EN	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
D7	castellated_edge · R7	gpio	GPIO1	D7, GPIO1, PWM, RX, PIO (any GPIO), SPI0_CSn, UART0_RX, I2C0_SCL, PWM0_B, SIO, PIO0, PIO1, USB_VBUS_DET	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	≤ 3.3 V	RP2040 datasheet p.617 table 617_1
SWDIO	back_pads · TP5	debug	SWD	SWDIO	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	-0.5–3.8 V	RP2040 datasheet p.617 table 617_1
SWCLK	back_pads · TP3	debug	SWCLK	SWCLK	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	-0.5–3.8 V	RP2040 datasheet p.617 table 617_1
RUN	back_pads · TP1	control	RUN	RUN	2–3.6 V	-0.3–0.8 V	2.62–3.3 V	0–0.5 V	≤ 12 mA	≤ 12 mA	no	-0.5–3.8 V	RP2040 datasheet p.617 table 617_1
GND_TP	back_pads · TP6	ground		ground
VIN	back_pads · VIN0	power in		power_in									p.4 table 4_1
GND_VIN	back_pads · GND0	ground		ground

Answers from the record

Seeed Studio XIAO RP2040 pinout FAQ

What microcontroller does the Seeed Studio XIAO RP2040 use?

The Seeed Studio XIAO RP2040 is built around the RP2040, alongside P25Q16SH (2 MB), LDO (DFN 1×1, part value not given).

How many GPIO pins does the Seeed Studio XIAO RP2040 have?

11 GPIO pins are exposed. Xirkit documents 20 board pins, 14 of them with pin-level electrical limits.

Are the Seeed Studio XIAO RP2040 I/O pins 5 V tolerant?

No. The I/O pins are not 5 V tolerant — they run at 3.3 V logic; use a level shifter for 5 V signals. Input-high threshold: 2–3.6 V.

How much current can a Seeed Studio XIAO RP2040 GPIO pin source?

Documented output-high current per pin: ≤ 12 mA. Values are traced to the chip datasheet; see the pinout table for per-pin limits and conditions.

What voltage powers the Seeed Studio XIAO RP2040?

Supply range 5–5 V. Power inputs: 5V, VIN.

Go deeper

Looking for something else? Browse every structured part.