Connected IoT devices and wireless sensor nodes
On-board radio: Wi-Fi 802.11 b/g/n 2.4 GHz.
Engineering inference
NodeMCU (open hardware; generic makers)
NodeMCU DEVKIT V1.0 is the open-hardware ESP8266 board: an ESP-12E module (ESP8266EX, 80/160 MHz, 4 MB flash, 802.11 b/g/n) with a CP2102 USB-serial on micro-USB. It has 30 pins on two 1×15 headers 0.9 in apart: D0–D8, RX/TX, A0 and SD0–SD3. There are FLASH and RST buttons, a blue LED on D0 / GPIO16 and 3.3 V logic. The board is 25.4 × 48.3 mm with four Ø2.9 mm holes and costs about .
NodeMCU DEVKIT V1.0Development boardFacts about the complete product. Unknown values remain open design questions.
Guidance to help you shortlist. The basis is shown for each recommendation.
On-board radio: Wi-Fi 802.11 b/g/n 2.4 GHz.
Engineering inferencePrograms from Arduino IDE, NodeMCU Lua firmware.
Engineering inferenceThe board is the parent product. Each chip has its own memory, pins, capabilities and thermal limits.
Espressif Systems
1956154e-b234-5b7f-ada0-dd840ece9977--mcuSilicon Labs
1956154e-b234-5b7f-ada0-dd840ece9977--u2Generated from the datasheet's dimensioned drawing and measured against it. Download the STEP to check fit in your own enclosure.
thickness=1.6 mm assumed: PCB thickness not in the Gerber or BOM; 1.6 mm assumed for the CAD envelope only
30 board pins and 20 explicit routes documented. The record marks the pinout complete. Alternate functions can share pins and may not be usable together.
Board connector positions are the physical points you wire to.
| Board pin | Connector / position | Electrical | Functions / constraints |
|---|---|---|---|
| A0ID L1 | J1 (A0 side)Position L1 | analog | A0 (10-bit, 0–3.3 V per Components101) ADC0 / TOUT |
| RSVID L2 | J1 (A0 side)Position L2 | other | rsv reserved |
| RSVID L3 | J1 (A0 side)Position L3 | other | rsv reserved |
| SD3ID L4 | J1 (A0 side)Position L4 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_DATA_3, SPIWP (flash) GPIO10, SDD3 (flash) |
| SD2ID L5 | J1 (A0 side)Position L5 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_DATA_2, SPIHD (flash) GPIO9, SDD2 (flash) |
| SD1ID L6 | J1 (A0 side)Position L6 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_DATA1, SPID/MOSI (flash), U1RXD MOSI, SDD1 (flash) |
| CMDID L7 | J1 (A0 side)Position L7 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_CMD, SPICS0 (flash) CS, SDCMD (flash) |
| SD0ID L8 | J1 (A0 side)Position L8 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_DATA0, SPIQ/MISO (flash) MISO, SDD0 (flash) |
| CLKID L9 | J1 (A0 side)Position L9 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | SDIO_CLK, SPICLK (flash) SCLK, SDCLK (flash) |
| GNDID L10 | J1 (A0 side)Position L10 | 0 Vground | ground ground |
| 3V3ID L11 | J1 (A0 side)Position L11 | power out | power_out 3.3 V |
| ENID L12 | J1 (A0 side)Position L12 | control | en chip enable |
| RSTID L13 | J1 (A0 side)Position L13 | control | rst reset |
| GNDID L14 | J1 (A0 side)Position L14 | 0 Vground | ground ground |
| VinID L15 | J1 (A0 side)Position L15 | power in | power_in VIN 5 V |
| D0ID R1 | J2 (D0 side)Position R1 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | blue onboard LED (LED_BUILTIN), Deep-sleep wakeup (connect to EXT_RSTB) GPIO16, USER LED, WAKE |
| D1ID R2 | J2 (D0 side)Position R2 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | IR Rx GPIO5 |
| D2ID R3 | J2 (D0 side)Position R3 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | PWM3 GPIO4 |
| D3ID R4 | J2 (D0 side)Position R4 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | FLASH button, SPICS2 GPIO0, FLASH button |
| D4ID R5 | J2 (D0 side)Position R5 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | I2C_SDA (software I2C), U1TXD, I2SO_WS GPIO2, TXD1 |
| 3V3ID R6 | J2 (D0 side)Position R6 | power out | power_out 3.3 V |
| GNDID R7 | J2 (D0 side)Position R7 | 0 Vground | ground ground |
| D5ID R8 | J2 (D0 side)Position R8 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | HSPICLK, I2C_SCL (software I2C), I2SI_WS, PWM2, IR TX GPIO14, HSCLK |
| D6ID R9 | J2 (D0 side)Position R9 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | HSPIQ/MISO, I2SI_DATA, PWM0 GPIO12, HMISO |
| D7ID R10 | J2 (D0 side)Position R10 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | HSPID/MOSI, U0CTS, I2SI_BCK GPIO13, RXD2, HMOSI |
| D8ID R11 | J2 (D0 side)Position R11 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | HSPICS, U0RTS, I2SO_BCK, PWM1 GPIO15, TXD2, HCS |
| RXID R12 | J2 (D0 side)Position R12 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | U0RXD, I2SO_DATA D9: GPIO3, RXD0 |
| TXID R13 | J2 (D0 side)Position R13 | 3.3 Vgpio5 V tolerant: noMax drive 12 mA | U0TXD, SPICS1 D10: GPIO1, TXD0 |
| GNDID R14 | J2 (D0 side)Position R14 | 0 Vground | ground ground |
| 3V3ID R15 | J2 (D0 side)Position R15 | power out | power_out 3.3 V |
A board label, a chip signal ID and a package lead number are different identifiers.
| Board connection | Chip instance | Chip signal | Package lead | Route |
|---|---|---|---|---|
L1 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | TOUTID TOUT | — | other scaled on board |
L4 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO10ID GPIO10 | — | direct |
L5 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO9ID GPIO9 | — | direct |
L6 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO8ID GPIO8 | — | direct |
L7 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO11ID GPIO11 | — | direct |
L8 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO7ID GPIO7 | — | direct |
L9 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO6ID GPIO6 | — | direct |
L12 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | CHIP_ENID CHIP_EN | — | direct |
L13 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | EXT_RSTBID EXT_RSTB | — | direct |
R1 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO16ID GPIO16 | — | direct |
R2 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO5ID GPIO5 | — | direct |
R3 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO4ID GPIO4 | — | direct |
R4 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO0ID GPIO0 | — | direct |
R5 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO2ID GPIO2 | — | direct |
R8 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO14ID GPIO14 | — | direct |
R9 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO12ID GPIO12 | — | direct |
R10 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO13ID GPIO13 | — | direct |
R11 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO15ID GPIO15 | — | direct |
R12 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO3ID GPIO3 | — | direct |
R13 | ESP8266EXInstance 1956154e-b234-5b7f-ada0-dd840ece9977--mcu | GPIO1ID GPIO1 | — | direct |
Chip signals stay attached to their chip instance, including their package lead and board exposure.
Chip package pins have not been transcribed for this instance.
Chip signals stay attached to their chip instance, including their package lead and board exposure.
Chip package pins have not been transcribed for this instance.
Supply voltage and GPIO logic voltage describe different parts of the design.
| Input | Voltage range | Connector | Notes |
|---|---|---|---|
| Vin | 7 to 12 V | — | VIN 5 V |
A 5 V supply input does not establish 5 V tolerance on GPIO. Check the documented power input and logic domain for each connection.
These describe the assembled board. Interface counts do not guarantee simultaneous operation.
| Interface | Support | Count | Details |
|---|---|---|---|
| adc | Documented | 1 | L1count stated in datasheet (adc_channels) |
| sdio | Documented | Unknown | L4, L5, L6, L7, L8, L9 |
| spi | Documented | Unknown | L4, L5, L6, L7, L8, L9, R4, R8, R9, R10, R11, R13 |
| uart | Documented | 1 | L6, R5, R10, R11, R12, R13count stated in datasheet (uart_count) |
| led | Documented | Unknown | R1 |
| control | Documented | Unknown | R1, R4 |
| other | Documented | Unknown | R2, R8 |
| pwm | Documented | 10 | R3, R8, R9, R11count stated in datasheet (pwm_channels) |
| i2c | Documented | Unknown | R5, R8 |
| i2s | Documented | Unknown | R5, R8, R9, R10, R11, R12 |
| usb | Documented | 1 | micro-USB, CP2102 USB-serial bridge |
Board capacity includes installed memory; chip-local memory is listed separately under each processor.
Capacities use KiB / MiB (1024-based units). Firmware partitions and runtime allocations reduce application-available memory.
Product operating conditions, chip ambient ratings, package case limits and junction maxima remain separate.
Reported product dimensions may exclude protruding components. Unknown height does not establish a complete clearance envelope.
Attached generated geometry is an approximate envelope. A generated outline does not establish an electrically verified PCB footprint.
| ID / type | Pins | Pitch | Notes |
|---|---|---|---|
| usbmicro-USB (Micro-B female) to the CP2102 USB-serial bridge | Unknown | Unknown | — |
| headers2 × 1×15 male pin headers, 2.54 mm pitch, rows 0.9 in (22.86 mm) apart | 30 | 2.54 mm | — |
Every available field, including details beyond the summaries. Null means the value has not been established.
US / USD is the target market. Observed price and stock are separate from a delivery quote.
US · USD
This observation is stale or has no verified check time. Recheck with the supplier.
Visit supplier (opens in a new tab)Delivery depends on quantity, postal code and shipping method. A dispatch statement such as “ship today” is not an arrival estimate.
Each source keeps its own verification status. Confirm the part revision and file contents before using it in a design.
Manufacturer reference
Unverified reference
inspected: black PCB, ESP-12E (ESP8266MOD) shielded module with PCB antenna, CP2102 QFN, micro-USB, FLASH and RST buttons, 2×15 pins labelled D0 D1 D2 D3 D4 3V3 GND D5 D6 D7 D8 RX TX GND 3V3 / A0 RSV RSV SD3 SD2 SD1 CMD SD0 CLK GND 3V3 EN RST GND Vin; four corner holes; retailer photo
Generated asset
cad_check passed
Generated envelope geometry may also exist for this record. It does not replace manufacturer CAD or a verified electrical land pattern.
Document provenance, retrieval dates and the field groups supported by each source.
Supports: spec.constraints.electrical.io_voltage_v, spec.constraints.electrical.logic_high_min_v, spec.constraints.electrical.pin_drive_max_ma, spec.constraints.electrical.supply_voltage_max_v, spec.constraints.electrical.supply_voltage_min_v, spec.geometry.cad.assumptions, spec.geometry.cad.bbox.height_mm, spec.geometry.cad.bbox.length_mm, spec.geometry.cad.bbox.width_mm, spec.geometry.cad.envelope_complete, spec.geometry.cad.mesh_path, spec.geometry.cad.step_path, spec.geometry.cad.verification, spec.geometry.dimensions.length_mm, spec.geometry.dimensions.width_mm, spec.geometry.mounting_holes, spec.provides.capabilities, spec.provides.features, spec.provides.gpio_count, spec.provides.memory.flash_kb, spec.provides.memory.sram_kb, spec.provides.software_frameworks, spec.provides.wireless, spec.usage.connectors, spec.usage.pin_mappings, spec.usage.pinout, spec.usage.pinout_complete, spec.usage.requirements.power_inputs
sha256 588efea35941080143af50fa562586067e4a9a4eb6cd553c571b3bbca1a64481
Supports: offers
The NodeMCU V1.0 ESP8266 (ESP-12E) Board is built around the ESP8266EX, alongside CP2102.
11 GPIO pins are exposed. Xirkit documents 30 board pins, 17 of them with pin-level electrical limits.
No. The I/O pins are not 5 V tolerant — they run at 3.3 V logic; use a level shifter for 5 V signals. Input-high threshold: 2.475–3.6 V.
Documented output-high current per pin: ≤ 12 mA. Values are traced to the chip datasheet; see the pinout table for per-pin limits and conditions.
Supply range 7–12 V. Power inputs: Vin (7–12 V).
From $6.95 at protosupplies.com. Prices are observed unit prices before tax and shipping.
48.26 × 25.4 mm. A STEP model is available for enclosure fit checks.
adc, sdio, spi, uart, led, control, other, pwm, i2c, i2s, usb.
Supported frameworks: Arduino IDE, NodeMCU Lua firmware.
Every value in this record is traced to a source — 2 documents including the board and chip datasheets — with the page and table cited per value. Unknowns are left explicit, never guessed.